As more devices are attached to the main memory bus in a computer system, there is more contention for use of the bus. In response to such contention, many different arbitration circuits have been proposed in order to give either fair access or priority access to the bus and thus, to memory resources.
For example, U.S. Pat. No. 5,195,185, which issued in the name of G. B. Marenin on Mar. 16, 1993, discloses an arbitration device which determines bus access based on a priority scheme, and also has a system to dynamically change the priority of any device. This system does not, however, provide flexibility in the basic arbitration scheme; it only responds to a device's increase of its own priority. It also cannot take into account which device previously used the bus in order to give either parity or priority to the other users. Finally, this system is locked into the priority scheme; it cannot be changed from a priority to a parity scheme when appropriate.
A further bus priority scheme is described in U.S. Pat. No. 4,979,100, which issued in the name of Makris, et al., on Dec. 18, 1990. Makris discloses an arbiter circuit which provides two different levels of priority of access to the bus for each processing unit and keeps track of the relative percentages of time of access for the different priority levels. This system provides for interruption of lower priority bus usage by higher priority process units. This system requires complicated overhead to track such bus usage, and is not responsive to previous bus usage by any one system.
Neither of these systems provides for flexible, dynamically changeable arbitration systems which can start in a known state and change from one arbitration scheme to another as conditions change, nor do they react to the past allocation. Therefore, a problem in the art is that there is no bus usage arbiter that provides a dynamic priority scheme with provisions for historical feedback in its grant selection.